diff --git a/Makefile b/Makefile
index 87616f0..3bd3964 100644
--- a/Makefile
+++ b/Makefile
@@ -11,6 +11,9 @@ objects := $(patsubst src/%, $(buildDir)/%, $(patsubst %.cpp, %.o, $(sources)))
 depends := $(patsubst %.o, %.d, $(objects))
 compileFlags := -std=c++17 -I include
 linkFlags = -L lib/$(platform) -l raylib
+ifdef MACRO_DEFS
+    macroDefines := -D $(MACRO_DEFS)
+endif
 
 # Check for Windows
 ifeq ($(OS), Windows_NT)
@@ -85,7 +88,7 @@ $(target): $(objects)
 # Compile objects to the build directory
 $(buildDir)/%.o: src/%.cpp Makefile
 	$(MKDIR) $(call platformpth, $(@D))
-	$(CXX) -MMD -MP -c $(compileFlags) $< -o $@
+	$(CXX) -MMD -MP -c $(compileFlags) $< -o $@ $(macroDefines)
 
 # Run the executable
 execute:
diff --git a/README.md b/README.md
index fb69f4b..8b8867e 100644
--- a/README.md
+++ b/README.md
@@ -91,6 +91,21 @@ $ make ARGS="--somearg"
 > mingw32-make ARGS="--somearg"
 ```
 
+### Specifying Custom Macro Definitions
+You may also want to pass in your own macro definitions for certain configurations (such as setting log levels). You can pass in your definitions using the `MACRO_DEFS` flag:
+
+#### macOS & Linux
+
+```console
+$ make MACRO_DEFS=MY_MACRO
+```
+
+#### Windows
+
+```console
+> mingw32-make MACRO_DEFS=MY_MACRO
+```
+
 ### Specifying a Non-Default Compiler
 If you want to use a compiler for your platform that isn't the default for your system (or potentially you would like to explicitly state it), you can make use of the system-implicit `CXX` variable like so:
 
diff --git a/docs/MakefileExplanation.md b/docs/MakefileExplanation.md
index b3c8525..961ecc3 100644
--- a/docs/MakefileExplanation.md
+++ b/docs/MakefileExplanation.md
@@ -35,9 +35,12 @@ objects := $(patsubst src/%, $(buildDir)/%, $(patsubst %.cpp, %.o, $(sources)))
 depends := $(patsubst %.o, %.d, $(objects))
 compileFlags := -std=c++17 -I include
 linkFlags = -L lib/$(platform) -l raylib
+ifdef MACRO_DEFS
+    macroDefines := -D $(MACRO_DEFS)
+endif
 ```
 
-In this snippet there are two different assignment operators used, `:=` meaning "instant, static assign", and `=` meaning lazy assign, where the macro will only be assigned on use (this is useful when it relies on another macro that may not yet be defined). The operator `?=` is also used in cases where assignment is contingent on the variable being previously undefined. Finally, the `+=` operator is used to append content to a previously defined macro.
+In this snippet there are two different assignment operators used, `:=` meaning "instant, static assign", and `=` meaning lazy assign, where the macro will only be assigned on use (this is useful when it relies on another macro that may not yet be defined). The operator `?=` is also used in cases where assignment is contingent on the variable being previously undefined. Finally, the `+=` operator is used to append content to a previously defined macro. At the very end, it checks to see if any macros were defined in the `Makefile` declaration and adds them to our compilation steps.
 
 ### Platform-Specific Macros
 The final grouping of macros in the Makefile relate to those that differ on a per-platform basis. The structure uses nested if-statements to first determine whether the current platform is Windows or not to assign macros. If it is not Windows, it then checks whether the current platform is Linux or macOS and assigns macros accordingly.
@@ -157,11 +160,11 @@ $(target): $(objects)
 	$(CXX) $(objects) -o $(target) $(linkFlags)
 ```
 
-As such, the target `$(buildDir)/%.o` is responsible for ensuring the creation and update of object files (`.o` files). The target will create all necessary subdirectory structures needed for the files, and then compile each `.cpp` file in the source directory into an object file using a number of rather terse, [automatic variables that you can read up on here](https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html).
+As such, the target `$(buildDir)/%.o` is responsible for ensuring the creation and update of object files (`.o` files). The target will create all necessary subdirectory structures needed for the files, and then compile each `.cpp` file in the source directory into an object file using a number of rather terse, [automatic variables that you can read up on here](https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html). Finally, it includes any custom macros that we defined for each of these files. 
 ```Makefile
 $(buildDir)/%.o: src/%.cpp Makefile
 	$(MKDIR) $(call platformpth, $(@D))
-	$(CXX) -MMD -MP -c $(compileFlags) $< -o $@
+	$(CXX) -MMD -MP -c $(compileFlags) $< -o $@ $(macroDefines)
 ```
 That all being said, there are still two dependancies for the target, the `.cpp` files, and the Makefile itself. One might wonder why either of these need to be dependencies, given that without them, there would be nothing to compile and no instructions with which to compile it, however there is definitely some intention behind this. Firstly, the aforementioned automatic variables of `$<` and `$@` require a list of dependencies to iterate through, and secondly, we want to make sure everything is up-to-date. For instance, changing a `.cpp` file should trigger this step to run again for that file, or changing the Makefile should warrant a full recompilation.