rename OP_MOVE -> OP_MOV
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parent
8f100ef3a0
commit
e478330109
14
src/asm.c
14
src/asm.c
@ -25,7 +25,7 @@ enum decode_error {
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};
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};
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enum operation {
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enum operation {
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OP_MOVE,
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OP_MOV,
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OP_ADD,
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OP_ADD,
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OP_SUB,
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OP_SUB,
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OP_CMP,
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OP_CMP,
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@ -197,7 +197,7 @@ static const char *operation_to_str(enum operation op) {
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static void instruction_to_str(char *buff, size_t max_size, struct instruction *inst) {
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static void instruction_to_str(char *buff, size_t max_size, struct instruction *inst) {
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switch (inst->op)
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switch (inst->op)
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{
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{
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case OP_MOVE:
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case OP_MOV:
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case OP_CMP:
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case OP_CMP:
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case OP_SUB:
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case OP_SUB:
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case OP_ADD: {
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case OP_ADD: {
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@ -345,7 +345,7 @@ enum decode_error decode_instruction(FILE *src, struct instruction *output) {
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u8 reg = (byte2 & 0b00111000) >> 3;
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u8 reg = (byte2 & 0b00111000) >> 3;
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u8 rm = byte2 & 0b00000111;
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u8 rm = byte2 & 0b00000111;
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output->op = OP_MOVE;
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output->op = OP_MOV;
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if (direction) {
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if (direction) {
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output->dest.is_reg = true;
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output->dest.is_reg = true;
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output->dest.reg = decode_reg(reg, wide);
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output->dest.reg = decode_reg(reg, wide);
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@ -361,7 +361,7 @@ enum decode_error decode_instruction(FILE *src, struct instruction *output) {
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bool wide = (byte1 & 0b1000) >> 3;
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bool wide = (byte1 & 0b1000) >> 3;
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u8 reg = byte1 & 0b111;
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u8 reg = byte1 & 0b111;
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output->op = OP_MOVE;
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output->op = OP_MOV;
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output->dest.is_reg = true;
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output->dest.is_reg = true;
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output->dest.reg = decode_reg(reg, wide);
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output->dest.reg = decode_reg(reg, wide);
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@ -381,7 +381,7 @@ enum decode_error decode_instruction(FILE *src, struct instruction *output) {
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u8 mod = (byte2 & 0b11000000) >> 6;
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u8 mod = (byte2 & 0b11000000) >> 6;
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u8 rm = byte2 & 0b00000111;
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u8 rm = byte2 & 0b00000111;
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output->op = OP_MOVE;
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output->op = OP_MOV;
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decode_reg_or_mem(&output->dest, src, rm, mod, wide);
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decode_reg_or_mem(&output->dest, src, rm, mod, wide);
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if (wide) {
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if (wide) {
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@ -394,7 +394,7 @@ enum decode_error decode_instruction(FILE *src, struct instruction *output) {
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// MOVE: Memory to accumulator
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// MOVE: Memory to accumulator
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} else if ((byte1 & 0b11111110) == 0b10100000) {
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} else if ((byte1 & 0b11111110) == 0b10100000) {
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output->op = OP_MOVE;
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output->op = OP_MOV;
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output->dest.is_reg = true;
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output->dest.is_reg = true;
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output->dest.reg = REG_AX;
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output->dest.reg = REG_AX;
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output->src.variant = SRC_VALUE_MEM;
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output->src.variant = SRC_VALUE_MEM;
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@ -411,7 +411,7 @@ enum decode_error decode_instruction(FILE *src, struct instruction *output) {
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} else if ((byte1 & 0b11111110) == 0b10100010) {
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} else if ((byte1 & 0b11111110) == 0b10100010) {
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bool wide = byte1 & 0b1;
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bool wide = byte1 & 0b1;
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output->op = OP_MOVE;
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output->op = OP_MOV;
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output->src.variant = SRC_VALUE_REG;
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output->src.variant = SRC_VALUE_REG;
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output->src.reg = wide ? REG_AX : REG_AL;
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output->src.reg = wide ? REG_AX : REG_AL;
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output->dest.is_reg = false;
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output->dest.is_reg = false;
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