Simulate non-memory MOVs
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0b57a4fed2
commit
6794570362
2
.vscode/c_cpp_properties.json
vendored
2
.vscode/c_cpp_properties.json
vendored
@ -15,7 +15,7 @@
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"windowsSdkVersion": "10.0.22000.0",
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"compilerPath": "C:/MinGW/bin/gcc.exe",
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"cStandard": "c17",
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"cppStandard": "c++17",
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"cppStandard": "c++11",
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"intelliSenseMode": "windows-gcc-x86",
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"configurationProvider": "ms-vscode.makefile-tools"
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}
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27
examples/immediate_movs.asm
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27
examples/immediate_movs.asm
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@ -0,0 +1,27 @@
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; ========================================================================
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;
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; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
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;
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; This software is provided 'as-is', without any express or implied
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; warranty. In no event will the authors be held liable for any damages
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; arising from the use of this software.
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;
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; Please see https://computerenhance.com for further information
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;
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; ========================================================================
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; ========================================================================
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; LISTING 43
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; ========================================================================
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bits 16
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mov ax, 1
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mov bx, 2
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mov cx, 3
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mov dx, 4
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mov sp, 5
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mov bp, 6
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mov si, 7
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mov di, 8
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19
examples/immediate_movs.txt
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examples/immediate_movs.txt
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@ -0,0 +1,19 @@
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--- test\listing_0043_immediate_movs execution ---
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mov ax, 1 ; ax:0x0->0x1
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mov bx, 2 ; bx:0x0->0x2
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mov cx, 3 ; cx:0x0->0x3
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mov dx, 4 ; dx:0x0->0x4
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mov sp, 5 ; sp:0x0->0x5
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mov bp, 6 ; bp:0x0->0x6
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mov si, 7 ; si:0x0->0x7
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mov di, 8 ; di:0x0->0x8
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Final registers:
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ax: 0x0001 (1)
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bx: 0x0002 (2)
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cx: 0x0003 (3)
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dx: 0x0004 (4)
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sp: 0x0005 (5)
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bp: 0x0006 (6)
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si: 0x0007 (7)
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di: 0x0008 (8)
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32
examples/register_movs.asm
Normal file
32
examples/register_movs.asm
Normal file
@ -0,0 +1,32 @@
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; ========================================================================
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;
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; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
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;
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; This software is provided 'as-is', without any express or implied
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; warranty. In no event will the authors be held liable for any damages
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; arising from the use of this software.
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;
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; Please see https://computerenhance.com for further information
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;
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; ========================================================================
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; ========================================================================
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; LISTING 44
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; ========================================================================
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bits 16
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mov ax, 1
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mov bx, 2
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mov cx, 3
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mov dx, 4
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mov sp, ax
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mov bp, bx
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mov si, cx
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mov di, dx
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mov dx, sp
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mov cx, bp
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mov bx, si
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mov ax, di
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23
examples/register_movs.txt
Normal file
23
examples/register_movs.txt
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@ -0,0 +1,23 @@
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--- test\listing_0044_register_movs execution ---
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mov ax, 1 ; ax:0x0->0x1
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mov bx, 2 ; bx:0x0->0x2
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mov cx, 3 ; cx:0x0->0x3
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mov dx, 4 ; dx:0x0->0x4
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mov sp, ax ; sp:0x0->0x1
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mov bp, bx ; bp:0x0->0x2
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mov si, cx ; si:0x0->0x3
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mov di, dx ; di:0x0->0x4
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mov dx, sp ; dx:0x4->0x1
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mov cx, bp ; cx:0x3->0x2
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mov bx, si ; bx:0x2->0x3
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mov ax, di ; ax:0x1->0x4
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Final registers:
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ax: 0x0004 (4)
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bx: 0x0003 (3)
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cx: 0x0002 (2)
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dx: 0x0001 (1)
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sp: 0x0001 (1)
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bp: 0x0002 (2)
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si: 0x0003 (3)
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di: 0x0004 (4)
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24
src/main.c
24
src/main.c
@ -107,7 +107,29 @@ int dissassemble(FILE *src, FILE *dst) {
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}
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int simulate(FILE *src) {
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todo("simulate");
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struct cpu_state state = { 0 };
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struct instruction inst;
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int counter = 1;
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while (true) {
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enum decode_error err = decode_instruction(src, &inst);
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if (err == DECODE_ERR_EOF) break;
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if (err != DECODE_OK) {
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fprintf(stderr, "ERROR: Failed to decode %d instruction: %s\n", counter, decode_error_to_str(err));
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return -1;
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}
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execute_instruction(&state, &inst);
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counter += 1;
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}
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printf("Final registers:\n");
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printf(" ax: 0x%04x (%d)\n", state.ax, state.ax);
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printf(" bx: 0x%04x (%d)\n", state.bx, state.bx);
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printf(" cx: 0x%04x (%d)\n", state.cx, state.cx);
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printf(" sp: 0x%04x (%d)\n", state.sp, state.sp);
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printf(" bp: 0x%04x (%d)\n", state.bp, state.bp);
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printf(" si: 0x%04x (%d)\n", state.si, state.si);
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printf(" di: 0x%04x (%d)\n", state.di, state.di);
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return 0;
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}
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void print_usage(const char *program) {
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@ -100,3 +100,14 @@ struct instruction {
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struct src_value src;
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i8 jmp_offset;
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};
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struct cpu_state {
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u16 ax;
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u16 bx;
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u16 cx;
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u16 dx;
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u16 sp;
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u16 bp;
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u16 si;
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u16 di;
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};
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@ -114,6 +114,7 @@ static void deocde_reg_or_mem_to_src(struct src_value *value, FILE *src, u8 rm,
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}
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}
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// TODO: change to readinf from a byte buffer
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// TODO: add handling for 'DECODE_ERR_MISSING_BYTES'
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// Handy reference: Table 4-12. 8086 Instruction Encoding
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enum decode_error decode_instruction(FILE *src, struct instruction *output) {
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@ -0,0 +1,106 @@
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u16 get_register_value(struct cpu_state *state, enum reg_value reg)
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{
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switch (reg)
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{
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case REG_AL: return state->ax & 0xFF;
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case REG_CL: return state->cx & 0xFF;
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case REG_DL: return state->dx & 0xFF;
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case REG_BL: return state->bx & 0xFF;
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case REG_AH: return (state->ax >> 8) & 0xFF;
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case REG_CH: return (state->cx >> 8) & 0xFF;
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case REG_DH: return (state->dx >> 8) & 0xFF;
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case REG_BH: return (state->bx >> 8) & 0xFF;
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case REG_AX: return state->ax;
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case REG_CX: return state->cx;
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case REG_DX: return state->dx;
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case REG_BX: return state->bx;
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case REG_SP: return state->sp;
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case REG_BP: return state->bp;
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case REG_SI: return state->si;
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case REG_DI: return state->di;
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default: panic("Unhandled register '%s'", reg_to_str(reg));
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}
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}
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void set_register_value(struct cpu_state *state, enum reg_value reg, u16 value)
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{
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switch (reg)
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{
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case REG_AL:
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state->ax = (state->ax & 0xFF00) & value;
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break;
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case REG_CL:
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state->cx = (state->cx & 0xFF00) & value;
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break;
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case REG_DL:
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state->dx = (state->dx & 0xFF00) & value;
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break;
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case REG_BL:
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state->bx = (state->bx & 0xFF00) & value;
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break;
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case REG_AH:
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state->ax = (state->ax & 0x00FF) & (value << 8);
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break;
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case REG_CH:
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state->cx = (state->cx & 0x00FF) & (value << 8);
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break;
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case REG_DH:
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state->dx = (state->dx & 0x00FF) & (value << 8);
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break;
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case REG_BH:
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state->bx = (state->bx & 0x00FF) & (value << 8);
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break;
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case REG_AX:
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state->ax = value;
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break;
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case REG_CX:
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state->cx = value;
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break;
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case REG_DX:
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state->dx = value;
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break;
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case REG_BX:
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state->bx = value;
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break;
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case REG_SP:
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state->sp = value;
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break;
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case REG_BP:
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state->bp = value;
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break;
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case REG_SI:
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state->si = value;
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break;
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case REG_DI:
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state->di = value;
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break;
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default:
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panic("Unhandled register '%s'", reg_to_str(reg));
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}
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}
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void execute_instruction(struct cpu_state *state, struct instruction *inst) {
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switch (inst->op)
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{
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case OP_MOV:
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if (!inst->dest.is_reg) {
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todo("Handle MOV to memory");
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}
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if (inst->src.variant == SRC_VALUE_MEM) {
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todo("Handle MOV from memory");
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}
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u16 src_value;
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if (inst->src.variant == SRC_VALUE_REG) {
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src_value = get_register_value(state, inst->src.reg);
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} else if (inst->src.variant == SRC_VALUE_IMMEDIATE8 || inst->src.variant == SRC_VALUE_IMMEDIATE16) {
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src_value = inst->src.immediate;
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}
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set_register_value(state, inst->dest.reg, src_value);
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break;
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default:
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todo("Unhandled instruction execution '%s'\n", operation_to_str(inst->op));
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}
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}
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