add decoding of add, sub, cmp and conditional jumps
This commit is contained in:
parent
5cfffd9dc9
commit
4535ee9adb
348
src/asm.c
348
src/asm.c
@ -18,15 +18,57 @@
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enum decode_error {
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DECODE_OK,
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DECODE_ERR_EOF,
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DECODE_ERR_MISSING_BYTES
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DECODE_ERR_MISSING_BYTES,
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DECODE_ERR_UNKNOWN_OP,
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};
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enum operation {
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OP_MOVE,
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OP_ADD,
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OP_SUB,
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OP_CMP,
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OP_JE, OP_JL, OP_JLE, OP_JB, OP_JBE,
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OP_JP,
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OP_JO,
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OP_JS,
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OP_JNE, OP_JNL, OP_JNLE, OP_JNB, OP_JNBE,
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OP_JNP,
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OP_JNO,
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OP_JNS,
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OP_LOOP,
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OP_LOOPZ,
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OP_LOOPNZ,
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OP_JCXZ,
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__OP_COUNT
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};
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const char *operation_str[__OP_COUNT] = {
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"mov"
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"mov", "add", "sub", "cmp", "je", "jl", "jle", "jb", "jbe", "jp", "jo",
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"js", "jne", "jnl","jnle", "jnb", "jnbe", "jnp", "jno", "jns", "loop",
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"loopz", "loopnz", "jcxz"
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};
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const enum operation cond_jmp_lookup[16] = {
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[0b0100] = OP_JE,
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[0b1100] = OP_JL,
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[0b1110] = OP_JLE,
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[0b0010] = OP_JB,
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[0b0110] = OP_JBE,
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[0b1010] = OP_JP,
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[0b0000] = OP_JO,
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[0b1000] = OP_JS,
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[0b0101] = OP_JNE,
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[0b1101] = OP_JNL,
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[0b1111] = OP_JNLE,
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[0b0011] = OP_JNB,
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[0b0111] = OP_JNBE,
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[0b1011] = OP_JNP,
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[0b0001] = OP_JNO,
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[0b1001] = OP_JNS
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};
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const enum operation cond_loop_jmp_lookup[4] = {
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[0b10] = OP_LOOP,
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[0b01] = OP_LOOPZ,
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[0b00] = OP_LOOPNZ,
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[0b11] = OP_JCXZ
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};
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// Order and place of these `enum reg_value` enums is IMPORTANT! Don't rearrange!
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@ -81,8 +123,8 @@ struct reg_or_mem_value {
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enum src_value_variant {
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SRC_VALUE_REG,
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SRC_VALUE_MEM,
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SRC_VALUE_IMMIDIATE8,
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SRC_VALUE_IMMIDIATE16
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SRC_VALUE_immediate8,
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SRC_VALUE_immediate16
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};
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struct src_value {
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@ -90,7 +132,7 @@ struct src_value {
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union {
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enum reg_value reg;
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struct mem_value mem;
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u16 immidiate;
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u16 immediate;
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};
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};
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@ -98,6 +140,7 @@ struct instruction {
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enum operation op;
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struct reg_or_mem_value dest;
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struct src_value src;
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i8 jmp_offset;
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};
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static const char *reg_to_str(enum reg_value reg) {
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@ -135,11 +178,11 @@ static void src_to_str(char *buff, size_t max_size, struct src_value *value) {
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case SRC_VALUE_MEM:
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mem_to_str(buff, max_size, &value->mem);
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break;
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case SRC_VALUE_IMMIDIATE16:
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snprintf(buff, max_size, "%d", value->immidiate);
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case SRC_VALUE_immediate16:
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snprintf(buff, max_size, "%d", value->immediate);
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break;
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case SRC_VALUE_IMMIDIATE8:
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snprintf(buff, max_size, "%d", (u8)value->immidiate);
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case SRC_VALUE_immediate8:
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snprintf(buff, max_size, "%d", (u8)value->immediate);
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break;
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}
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}
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@ -152,19 +195,52 @@ static const char *operation_to_str(enum operation op) {
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static void instruction_to_str(char *buff, size_t max_size, struct instruction *inst) {
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switch (inst->op)
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{
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case OP_MOVE: {
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char dest[24];
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char src[24];
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case OP_MOVE:
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case OP_CMP:
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case OP_SUB:
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case OP_ADD: {
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char dest[32];
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char src[32];
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const char *opcode = operation_to_str(inst->op);
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reg_or_mem_to_str(dest, sizeof(dest), &inst->dest);
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src_to_str(src, sizeof(src), &inst->src);
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bool is_dest_mem = !inst->dest.is_reg;
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if (is_dest_mem && inst->src.variant == SRC_VALUE_IMMIDIATE16) {
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snprintf(buff, max_size, "mov %s, word %s", dest, src);
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} else if (is_dest_mem && inst->src.variant == SRC_VALUE_IMMIDIATE8) {
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snprintf(buff, max_size, "mov %s, byte %s", dest, src);
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if (is_dest_mem && inst->src.variant == SRC_VALUE_immediate16) {
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snprintf(buff, max_size, "%s %s, word %s", opcode, dest, src);
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} else if (is_dest_mem && inst->src.variant == SRC_VALUE_immediate8) {
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snprintf(buff, max_size, "%s %s, byte %s", opcode, dest, src);
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} else {
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snprintf(buff, max_size, "mov %s, %s", dest, src);
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snprintf(buff, max_size, "%s %s, %s", opcode, dest, src);
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}
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break;
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}
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case OP_JE:
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case OP_JL:
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case OP_JLE:
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case OP_JB:
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case OP_JBE:
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case OP_JP:
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case OP_JO:
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case OP_JS:
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case OP_JNE:
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case OP_JNL:
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case OP_JNLE:
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case OP_JNB:
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case OP_JNBE:
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case OP_JNP:
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case OP_JNO:
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case OP_LOOP:
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case OP_LOOPZ:
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case OP_LOOPNZ:
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case OP_JCXZ:
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case OP_JNS: {
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const char *opcode = operation_to_str(inst->op);
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i8 offset = inst->jmp_offset+2;
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if (offset >= 0) {
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snprintf(buff, max_size, "%s $+%d", opcode, offset);
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} else {
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snprintf(buff, max_size, "%s $%d", opcode, offset);
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}
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break;
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}
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@ -181,6 +257,22 @@ static i16 extend_sign_bit(i8 number) {
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}
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}
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const char *decode_error_to_str(enum decode_error err) {
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switch (err)
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{
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case DECODE_OK:
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return "ok";
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case DECODE_ERR_EOF:
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return "EOF";
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case DECODE_ERR_MISSING_BYTES:
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return "Decoder expected more bytes, but hit EOF";
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case DECODE_ERR_UNKNOWN_OP:
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return "Unable to decode opcode from byte";
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default:
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return "<unknown>";
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}
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}
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// This function assumes that the `enum reg_value` values are in a convenient order, for conversion.
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// Look at "Table 4-9. REG (Register) Field Encoding" for more details
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static enum reg_value decode_reg(u8 reg, bool wide) {
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@ -195,20 +287,20 @@ static enum mem_base decode_mem_base(u8 rm) {
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// Table 4-10. R/M (Register/Memory) Field Encoding
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static void decode_reg_or_mem(struct reg_or_mem_value *value, FILE *src, u8 rm, u8 mod, bool wide) {
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if (mod == 0b11000000) { // Mod = 0b11, register
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if (mod == 0b11) { // Mod = 0b11, register
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value->is_reg = true;
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value->reg = decode_reg(rm, wide);
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} else if (mod == 0b10000000) { // Mod = 0b10, memory with i16 displacement
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} else if (mod == 0b10) { // Mod = 0b10, memory with i16 displacement
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i16 displacement = fgetc(src) | (fgetc(src) << 8);
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value->is_reg = false;
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value->mem.base = decode_mem_base(rm);
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value->mem.disp = displacement;
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} else if (mod == 0b01000000) { // Mod = 0b01, memory with i8 displacement
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} else if (mod == 0b01) { // Mod = 0b01, memory with i8 displacement
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i8 displacement = fgetc(src);
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value->is_reg = false;
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value->mem.base = decode_mem_base(rm);
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value->mem.disp = extend_sign_bit(displacement);
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} else if (mod == 0b00000000) { // Mod = 0b00, memory no displacement (most of the time)
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} else if (mod == 0b00) { // Mod = 0b00, memory no displacement (most of the time)
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value->is_reg = false;
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if (rm == 0b110) { // Direct address
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u16 address = fgetc(src) | (fgetc(src) << 8);
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@ -241,15 +333,110 @@ enum decode_error decode_instruction(FILE *src, struct instruction *output) {
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u8 byte1 = fgetc(src);
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if (feof(src)) return DECODE_ERR_EOF;
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output->op = OP_MOVE;
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// Register memory to/from register
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// MOVE: Register memory to/from register
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if ((byte1 & 0b11111100) == 0b10001000) {
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u8 byte2 = fgetc(src);
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bool wide = byte1 & 0b1;
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bool direction = (byte1 & 0b10) >> 1;
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u8 mod = byte2 & 0b11000000;
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u8 mod = (byte2 & 0b11000000) >> 6;
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u8 reg = (byte2 & 0b00111000) >> 3;
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u8 rm = byte2 & 0b00000111;
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output->op = OP_MOVE;
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if (direction) {
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output->dest.is_reg = true;
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output->dest.reg = decode_reg(reg, wide);
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deocde_reg_or_mem_to_src(&output->src, src, rm, mod, wide);
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} else {
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output->src.variant = SRC_VALUE_REG;
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output->src.reg = decode_reg(reg, wide);
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decode_reg_or_mem(&output->dest, src, rm, mod, wide);
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}
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// MOVE: Immediate to register
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} else if ((byte1 & 0b11110000) == 0b10110000) {
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bool wide = (byte1 & 0b1000) >> 3;
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u8 reg = byte1 & 0b111;
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output->op = OP_MOVE;
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output->dest.is_reg = true;
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output->dest.reg = decode_reg(reg, wide);
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if (wide) {
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output->src.variant = SRC_VALUE_immediate16;
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output->src.immediate = fgetc(src) | (fgetc(src) << 8);
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} else {
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output->src.variant = SRC_VALUE_immediate8;
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output->src.immediate = fgetc(src);
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}
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// MOVE: Immediate to register/memory
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} else if ((byte1 & 0b11111110) == 0b11000110) {
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u8 byte2 = fgetc(src);
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bool wide = byte1 & 0b1;
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u8 mod = (byte2 & 0b11000000) >> 6;
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u8 rm = byte2 & 0b00000111;
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output->op = OP_MOVE;
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decode_reg_or_mem(&output->dest, src, rm, mod, wide);
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if (wide) {
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output->src.variant = SRC_VALUE_immediate16;
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output->src.immediate = fgetc(src) | (fgetc(src) << 8);
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} else {
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output->src.variant = SRC_VALUE_immediate8;
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output->src.immediate = fgetc(src);
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}
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// MOVE: Memory to accumulator
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} else if ((byte1 & 0b11111110) == 0b10100000) {
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output->op = OP_MOVE;
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output->dest.is_reg = true;
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output->dest.reg = REG_AX;
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output->src.variant = SRC_VALUE_MEM;
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output->src.mem.base = MEM_BASE_DIRECT_ADDRESS;
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bool wide = byte1 & 0b1;
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if (wide) {
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output->src.mem.disp = fgetc(src) | (fgetc(src) << 8);
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} else {
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output->src.mem.disp = fgetc(src);
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}
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// MOVE: Accumulator to memory
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} else if ((byte1 & 0b11111110) == 0b10100010) {
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bool wide = byte1 & 0b1;
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output->op = OP_MOVE;
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output->src.variant = SRC_VALUE_REG;
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output->src.reg = wide ? REG_AX : REG_AL;
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output->dest.is_reg = false;
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output->dest.mem.base = MEM_BASE_DIRECT_ADDRESS;
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if (wide) {
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output->dest.mem.disp = fgetc(src) | (fgetc(src) << 8);
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} else {
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output->dest.mem.disp = fgetc(src);
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}
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// ADD/SUB/CMP: Reg/memory with register to either
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} else if ((byte1 & 0b11000100) == 0b00000000) {
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u8 variant = (byte1 & 0b00111000) >> 3;
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if (variant == 0b000) {
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output->op = OP_ADD;
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} else if (variant == 0b101) {
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output->op = OP_SUB;
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} else if (variant == 0b111) {
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output->op = OP_CMP;
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}
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bool wide = byte1 & 0b01;
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bool direction = (byte1 & 0b10) >> 1;
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u8 byte2 = fgetc(src);
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u8 mod = (byte2 & 0b11000000) >> 6;
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u8 reg = (byte2 & 0b00111000) >> 3;
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u8 rm = byte2 & 0b00000111;
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@ -263,92 +450,103 @@ enum decode_error decode_instruction(FILE *src, struct instruction *output) {
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decode_reg_or_mem(&output->dest, src, rm, mod, wide);
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}
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// Immediate to register
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} else if ((byte1 & 0b11110000) == 0b10110000) {
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bool wide = (byte1 & 0b1000) >> 3;
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u8 reg = byte1 & 0b111;
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// ADD/SUB/CMP: immediate with register/memory
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} else if ((byte1 & 0b11111100) == 0b10000000) {
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u8 byte2 = fgetc(src);
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u8 variant = (byte2 & 0b00111000) >> 3;
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output->dest.is_reg = true;
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output->dest.reg = decode_reg(reg, wide);
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if (wide) {
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output->src.variant = SRC_VALUE_IMMIDIATE16;
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output->src.immidiate = fgetc(src) | (fgetc(src) << 8);
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} else {
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output->src.variant = SRC_VALUE_IMMIDIATE8;
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output->src.immidiate = fgetc(src);
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if (variant == 0b000) {
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output->op = OP_ADD;
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} else if (variant == 0b101) {
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output->op = OP_SUB;
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} else if (variant == 0b111) {
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output->op = OP_CMP;
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}
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// Immediate to register/memory
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} else if ((byte1 & 0b11111110) == 0b11000110) {
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u8 byte2 = fgetc(src);
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bool wide = byte1 & 0b1;
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u8 mod = byte2 & 0b11000000;
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bool wide = byte1 & 0b01;
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bool sign_extend = (byte1 & 0b10) >> 1;
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u8 mod = (byte2 & 0b11000000) >> 6;
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u8 rm = byte2 & 0b00000111;
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decode_reg_or_mem(&output->dest, src, rm, mod, wide);
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if (wide) {
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output->src.variant = SRC_VALUE_IMMIDIATE16;
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output->src.immidiate = fgetc(src) | (fgetc(src) << 8);
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output->src.variant = SRC_VALUE_immediate16;
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if (sign_extend) {
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output->src.immediate = fgetc(src);
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output->src.immediate = extend_sign_bit(output->src.immediate);
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} else {
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output->src.immediate = fgetc(src) | (fgetc(src) << 8);
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}
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} else {
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output->src.variant = SRC_VALUE_IMMIDIATE8;
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output->src.immidiate = fgetc(src);
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output->src.variant = SRC_VALUE_immediate8;
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output->src.immediate = fgetc(src);
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}
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// Memory to accumulator
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} else if ((byte1 & 0b11111110) == 0b10100000) {
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// ADD/SUB/CMP: immediate with accumulator
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} else if ((byte1 & 0b11000110) == 0b00000100) {
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bool wide = byte1 & 0b1;
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output->dest.is_reg = true;
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output->dest.reg = REG_AX;
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output->src.variant = SRC_VALUE_MEM;
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output->src.mem.base = MEM_BASE_DIRECT_ADDRESS;
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output->dest.reg = wide ? REG_AX : REG_AL;
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if (wide) {
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output->src.mem.disp = fgetc(src) | (fgetc(src) << 8);
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} else {
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output->src.mem.disp = fgetc(src);
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u8 variant = (byte1 & 0b00111000) >> 3;
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if (variant == 0b000) {
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output->op = OP_ADD;
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} else if (variant == 0b101) {
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output->op = OP_SUB;
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} else if (variant == 0b111) {
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output->op = OP_CMP;
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}
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// Accumulator to memory
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} else if ((byte1 & 0b11111110) == 0b10100010) {
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bool wide = byte1 & 0b1;
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output->src.variant = SRC_VALUE_REG;
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output->src.reg = REG_AX;
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output->dest.is_reg = false;
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output->dest.mem.base = MEM_BASE_DIRECT_ADDRESS;
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if (wide) {
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output->dest.mem.disp = fgetc(src) | (fgetc(src) << 8);
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output->src.variant = SRC_VALUE_immediate16;
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output->src.immediate = fgetc(src) | (fgetc(src) << 8);
|
||||
} else {
|
||||
output->dest.mem.disp = fgetc(src);
|
||||
output->src.variant = SRC_VALUE_immediate8;
|
||||
output->src.immediate = fgetc(src);
|
||||
}
|
||||
|
||||
// Conditional jumps
|
||||
} else if ((byte1 & 0b11110000) == 0b01110000) {
|
||||
i8 jmp_offset = fgetc(src);
|
||||
u8 opcode = byte1 & 0b00001111;
|
||||
output->op = cond_jmp_lookup[opcode];
|
||||
output->jmp_offset = jmp_offset;
|
||||
|
||||
// Conditional jumps
|
||||
} else if ((byte1 & 0b11111100) == 0b11100000) {
|
||||
i8 jmp_offset = fgetc(src);
|
||||
u8 opcode = byte1 & 0b00000011;
|
||||
output->op = cond_loop_jmp_lookup[opcode];
|
||||
output->jmp_offset = jmp_offset;
|
||||
|
||||
} else {
|
||||
todo("unhandled byte %d", byte1);
|
||||
return DECODE_ERR_UNKNOWN_OP;
|
||||
}
|
||||
|
||||
return DECODE_OK;
|
||||
}
|
||||
|
||||
void dissassemble(FILE *src, FILE *dst) {
|
||||
int dissassemble(FILE *src, FILE *dst) {
|
||||
fprintf(dst, "bits 16\n\n");
|
||||
|
||||
char line[256];
|
||||
char buff[256];
|
||||
struct instruction inst;
|
||||
int counter = 1;
|
||||
while (true) {
|
||||
enum decode_error err = decode_instruction(src, &inst);
|
||||
if (err == DECODE_ERR_EOF) break;
|
||||
if (err != DECODE_OK) {
|
||||
fprintf(stderr, "ERROR: Failed to decode instruction, code: %d\n", err);
|
||||
break;
|
||||
fprintf(stderr, "ERROR: Failed to decode %d instruction: %s\n", counter, decode_error_to_str(err));
|
||||
return -1;
|
||||
}
|
||||
|
||||
instruction_to_str(line, sizeof(line), &inst);
|
||||
fprintf(dst, line);
|
||||
instruction_to_str(buff, sizeof(buff), &inst);
|
||||
fprintf(dst, buff);
|
||||
fprintf(dst, "\n");
|
||||
counter += 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user